In conventional memories, multiple integrated memory circuits are sometimes packaged together in a module referred to as a multiple memory device module. For example, multiple integrated memory circuits implemented on one or more dies can be packaged together in a multiple memory device module such as a single in-line memory module (SIMM), a dual in-line memory module (DIMM) and a multi-chip memory module (MCM). Of course, other package types also work.
Each integrated memory circuit in a multiple memory device module typically has one or more optional function circuits which can be enabled if necessary. For example, a redundant memory cell in an integrated memory circuit can be enabled to replace an inoperable memory cell having an address which is typically determined during the manufacturing process. Another typical optional function circuit allows for fine tuning of the component values of circuit elements such as resistors and capacitors in an integrated memory circuit. These redundant memory elements or other optional function circuits are typically enabled by opening laser fuses or shorting anti-fuses. For this reason, the redundant elements or function circuits are generally enabled at the chip level before the chip has been placed in a module. If a defect is found in a memory chip once the chip has been placed in a module, either the memory chip must be removed from the module for enabling the redundant elements or function circuits or the redundant elements or function circuits must be enabled for all chips on the module. For these reasons, memory device repair and the selection of optional functions once memory chips have been assembled together in a module has not been feasible for individual memory chips.
One approach to enabling a function circuit in an integrated memory circuit packaged along with other integrated memory circuits in a multiple memory device module might be to apply a high voltage to one of the input terminals of the module. The high voltage would then generally be strobed into the module with an address strobe signal such as CAS, and would be applied to each integrated memory circuit in the module which shares the same address strobe signal. Within each integrated memory circuit receiving the high voltage, programmable elements, such as anti-fuses, would be blown by the high voltage to enable the desired function circuit.
Thus, for example, if the high voltage was applied to the inputs of a multiple memory device module receiving both a CAS1 signal and a CAS2 signal, and the high voltage was then strobed into the module with the CAS1 signal, then the high voltage would be applied to each integrated memory circuit in the module which shares the CAS1 signal. As a result, the desired function circuit would be enabled in each integrated memory circuit which shares the CAS1 signal. Of course, the CAS1 signal could only go to one integrated memory circuit, in which case only the desired function circuit in that integrated memory circuit would be enabled.
For the above reasons, it does not appear to be possible to enable a desired function circuit in only one integrated memory circuit in a multiple memory device module. In a typical multiple memory device module, each integrated memory circuit has its own memory array which includes memory cells arranged in rows and columns and associated redundant memory cells typically arranged in rows. If a memory cell in a row in one of the integrated memory circuits is inoperable, then the above-described approach to repairing the inoperable memory cell would be to replace the row it is in with an associated row of redundant memory cells. At the same time, however, this approach would also replace operable memory cells in the other integrated memory circuits in the multiple memory device module with their associated rows of redundant memory cells. Consequently, in a multiple memory device module having two integrated memory circuits which share the same CAS signal, a row in one of the integrated memory circuits would be replaced with an associated redundant row despite the fact that the replaced row is not faulty.
This inability to isolate a faulty row in a single integrated memory circuit in a multiple memory device module for replacement would reduce the rate of success for repairing multiple memory device modules, since each repair would cause many operable standard memory cells to be unnecessarily replaced. Thus, for example, in a multiple memory device module having eight integrated memory circuits, repairing one inoperable standard memory cell would result in the replacement of one row of standard memory cells in each of the eight integrated memory circuits with an associated redundant row. If there is a 99% chance associated with each redundant row that it does not contain an inoperable memory cell, then there is a (0.99.sup.8) or only a 92% chance that all eight redundant rows do not contain inoperable memory cells. During a typical manufacturing run of thousands of multiple memory device modules, the difference between a 99% rate of successful repair and a 92% rate is obviously of great significance.
Therefore, there is a need in the art for a circuit and method for advantageously enabling a function circuit, such as a redundant memory cell, in only one of the integrated memory circuits in a multiple memory device module. Such a circuit and method should, when used to repair multiple memory device modules with inoperable standard memory cells, provide an increased rate of successful repair.